High voltage lateral double diffused MOS (DMOS) transistors using a lightly doped drain (LDD) extension (or drift region) are well known in the art.
The various problems associated with high voltage lateral DMOS transistors are illustrated with reference to FIG. 1.
FIG. 1 shows a first generation N-channel LDD lateral DMOS transistor, wherein N- drift region 10 is formed below field oxide region 11, using a well known Local Oxidation of Silicon (LOCOS) technique. In this structure, N+ source region 12 and P+ body contact region 14 are shorted together by metal contact 16. Doped polysilicon gate 18 is formed above and insulated from P body region 20 and P-31 substrate 22. Gate oxide 24 insulates gate 18 from P body region 20 and P substrate 22.
Gate 18 inverts P body region 20 and P- substrate 22 just under gate oxide 24 to create a conducting ohmic channel between N+ source region 12 and N+ drain region 26 when gate 18 has a voltage applied to it above the threshold voltage of the device. N- drift region 10 effectively acts as a resistive extension of N+ drain region 26 when the device is biased to be in its on state.
When the device is in its off state, N- drift region 10 becomes totally or partially depleted and acts to spread the electric field, induced by the voltage differential between the high voltage applied to N+ drain region 26 and the low (e.g., ground) voltage applied to P- substrate 22, over the length of drift region 10. This increases the breakdown voltage of the device by reducing the maximum electric field intensity at the drift region/channel interface 28 (i.e., where drift region 10 meets substrate 22 under gate 18). Drift region 10 thus greatly increases the breakdown voltage of the device albeit with a sacrifice in on-resistance. If higher breakdown voltages are desired, the drift region is typically made longer. This, however, also results in higher on-resistance.
In FIG. 1, gate 18 is extended over field oxide region 11 so as to form field plate 30. Field plate 30, being at a low gate potential, causes the electric field at the drift region/channel interface 28 to be further reduced, thus easing the stress at the drift region/channel interface 28. Additionally, field plate 30 shields the drift region/channel interface 28 from fields produced by overhead interconnect lines.
To further compound the problem of designing a lateral DMOS device with high breakdown voltage but with small surface area and low on-resistance, faults in the crystalline structure at the interface of field oxide region 11 and the silicon exist due to the heating of the silicon during the LOCOS process used to form field oxide 11. This fault in the crystalline structure occurs due to the silicon and silicon nitride (used in the LOCOS process) from expanding at different rates during heating. Consequently, under the silicon nitride the silicon atoms in the crystalline structure are no longer aligned. This contributes to the bird's beak formation at the ends of LOCOS field oxide 11. This fault causes the crystalline structure to have a lower breakdown voltage. The difficulty in forming a high voltage lateral DMOS device is compounded by this problem since where this fault exists is also where the highest electric field exists, that is, at the drift region/channel interface 28.
Another problem in obtaining the desired manufacturing tolerances is that the mask for LOCOS field oxide 11 and gate 18 must be precisely aligned so that the channel region is of the desired length.
One reason for the desirability of the structure of FIG. 1 is that LOCOS field oxide 11 and drift region 10 are formed along with other LOCOS field oxide regions and doped regions which are not being used as drift regions. For example, elsewhere on a semiconductor wafer, an N region underlying a LOCOS field oxide region may be used to separate two P+ regions within an N-well. This N region under the LOCOS field oxide region would then prevent a parasitic MOS transistor from forming, preventing conduction between the two P+ regions due to, for example, an interconnect line passing over the N region carrying a high voltage. Without the N region between the two P+ regions, the line's electric field could invert the lightly doped N well region between the P+ regions causing the parasitic MOS transistor to turn on.
N- drift region 10 and overlying LOCOS field oxide 11 are formed using well-known techniques. Typically, N type dopants are implanted into the surface of the wafer through a mask and the wafer is subjected to a thermal oxide forming process until the LOCOS field oxide has reached the desired thickness.
The structure of FIG. 1 is typically formed as an annular device or a rectangular device concentric around center line CL through N+ drain 26. Thus, N+ source region 12 surrounds N+ drain 26.
A second generation N-channel LDD lateral DMOS transistor is shown in FIG. 2. This device performs essentially the same as the device of FIG. 1 except that N- drift region 10 is formed self-aligned with gate 18, using gate 18 as a mask, and field oxide 32 is formed over the entire surface of the wafer. By eliminating the formation of a LOCOS field oxide near the drift region/channel interface 28, there are no stress-created defects in the crystalline structure at the drift region/channel interface 28. Thus, the structure of FIG. 2 provides an improvement over the structure of FIG. 1. The various regions in FIG. 2 correspond in form and function to those in FIG. 1.
To reduce the electric field stress at the drift region/channel interface 28, field plate 34 is formed over the drift region/channel interface 28 and connected to gate or source potential.
As in the structure of FIG. 1, the structure of FIG. 2 is typically annular or rectangular shaped with a center line through drain region 26 and N+ source region 12 completely surrounding drain region 26.
Due to the annular shape of the DMOS device of FIG. 2, field plate 34 must be opened up to allow an interconnect line from outside the periphery of the DMOS device to contact drain region 26. Forming insulation over field plate 34 to insulate the interconnect line from field plate 34 is not desirable due to the added processing steps and time required to deposit a thick oxide insulator.
FIG. 3 shows a cross-section of the DMOS transistor of FIG. 2 in its off state at a portion where field plate 34 in FIG. 2 is opened to allow high voltage drain interconnect line 36 to extend through the periphery of the DMOS device to a high voltage terminal. Since interconnect line 36 is at a high voltage, and both P- substrate 22 and gate 18 are typically at ground potential, a high electric field exists between high voltage drain interconnect line 36 and both P- substrate 22 and gate 18. This high electric field causes field crowding in the vicinity of drift region/channel interface 28, as shown in FIG. 3. Thus, the DMOS device must be designed so that it does not break down even with this field crowding.
As an example of field crowding, without drain interconnect line 36 overlying N- drift region 10, the voltage at drift region/channel interface 28 is assumed to be 0.2 V.sub.d, where V.sub.d is the drain voltage. However, in the case where high voltage drain interconnect 36 is overlying N- drift region 10, the voltage at drift region/channel interface 28 may be as much as 0.7 V.sub.d. Exemplary equipotential lines are shown in FIG. 3, where the area with the most crowded lines is the area subject to the highest electric field. As seen, the area with the most crowded lines, and, hence, the area subject to the maximum stress, is in the vicinity of drift region/channel interface 28.
As a consequence of this field crowding, breakdown voltages of DMOS devices using interconnect lines, such as interconnect line 36 in FIG. 3, typically do not exceed 170 volts.
Making field oxide region 32, separating high voltage drain interconnect line 36 from N- drift region 10, thicker helps very little in reducing this high electric field. Thus, the breakdown voltage of the DMOS device of FIGS. 2 and 3 is limited by the portion of the DMOS device where the high voltage drain interconnect line 36 extends through the periphery of the DMOS device.